Infrared detector modules are used for a variety of purposes including space surveillance. In view of the stringent environmental and performance demands of such systems, as well as space limitations relating to launch and orbit, substantial needs have developed to miniaturize the modules while retaining high performance and high reliability of operation.
For example, in order to provide accurate resolution in infrared imaging it may be necessary to space infrared detector elements by 4 mils or less. It is also desirable to provide some form of focal plane signal processing in order to limit the need to communicate raw data to remote processors. Signal processing may comprise such functions as filtering, gain normalization, and amplification. Consequently, there has developed a need to provide an improved module structure which not only satisfies the dense connectivity problems but also permits on-focal plane processing of the raw input signals.
The use of Z plane stacked layer substrates for signal processing circuitry is common in the art, particularly for area detector arrays. Z Plane structures satisfy the requirements for detector array miniaturization and on-focal-plane signal processing. However, it does not by itself remedy problems involving mechanical and electrical interconnection to the detector array, and where detector operation of a cryogenic temperature is required, refrigeration of the larger mass of material is more difficultly obtained. In Z plane structures a plurality of devices such as semiconductor substrates or printed circuit boards are mechanically and electrically connected to the detector array. Each Z plane stack of substrates extends perpendicularly from the back surface of the detector array along an axis commonly designated as the Z axis in the art. The plane upon which circuitry is formed in Z plane mounting is perpendicular to the plane upon which detectors are formed. Many Z plane layer substrates can extend from a single detector array, thereby greatly increasing the available surface area for signal Processing circuitry. The Z plane structure is used because of the limited real estate, or surface area, available for integrated signal processing circuit fabrication upon the front and back surfaces of the detector array. The Z plane structure can extend a substantial distance beyond the plane of the detector array, thereby providing a significant increase in the surface area available for integrated circuit fabrication. Highly sensitive infrared detecting focal plane arrays typically employ different substrate materials, one for the detector array and another for the signal processing circuit. Z plane structures have been designed with ceramic layer substrates, silicon integrated circuits and CdTe detector array substrates. Assembly of the focal plane array then requires mechanical and electrical connections or bonds to be made between these different substrates. This method of assembly is often called a hybrid integrated circuit, as opposed to a monolithic integrated circuit, where a single substrate is used for the entire assembly. All the components are then totally integrated at a single unit. Since there are no mechanical or electrical bonds to be made, a higher degree of miniaturization can be obtained and many array elements and processing channels can be made by one set of fabrication processes. Such is the advancing state of the art for silicon monolithic integrated circuits.
The monolithic substrate in this invention is a large area, single crystalline wafer, such as readily available silicon. Graphotaxy, which is a form of epitaxy, where single crystalline films of the desired material so crystalline site laterally over polycrsytalline or amorphous structures. Detector arrays can then be made from single crystalline films of the desired material so formed on one side of the wafer and processor circuits on the other side. Stacked graphotaxially layers of silicon, for example, can then be used to provide sufficient areas for integrated circuit fabrication. The thickness of this processor stack made of thin film semiconductor layers separated by insulator films is many orders of magnitude less massive than stacked Z plane layers, which makes it far more acceptable for space borne applications.
Electrical connections between layers in the processor stack are readily made through windows in the insulator films. Electrical connections from the detector array to the processor circuits by an array of small diameter vias or electrical conduits through the wafer substrate. Prior art vias with diameters of 1/5 to 1/6 of the substrate thickness are common. Such vias are typically made by ether etching or laser drilling the substrate and then metalizing the resulting aperture. The use of vias having diameters in the range of 1/5 to 1/6 of the substrate thickness greatly reduces the available wafer surface area upon which detectors and signal processing circuitry can be fabricated. This is particularly true since the thickness of the wafer must be great enough to withstand the processing steps required to form the detector elements and signal processing circuitry. This prevents the use of a thin wafer which would permit correspondingly narrow vias.
The state of the art in both etching and laser drilling technology makes it extremely difficult to form long, thin vias. Sub-micron vias can be formed by either technique as long as they do not extend more than a few microns in length. Attempting to form vias having lengths in excess of a few microns results in flaring or misrouting of the vias due to inherent limitations in both the etching and laser drilling processes. Therefore, vias must have diameters proportional to the thickness of the substrate on which they are being formed in order to be formed true and parallel to their intended axes.
A monolithic focal plane array design having an array of extremely dense vias, with diameters in the one to twenty micron range is desirable. This permits the vias to be concentrated, thereby enabling a high density of detector elements. The vias must pass through wafers which are at least an order of magnitude thicker than the diameter of the vias. Such wafer thickness is required to maintain the mechanical integrity of the wafer through the detector and circuit fabrication Processes. The ability to form a dense array of such small diameter vias through a substrate which is at least an order of magnitude thicker than the via diameter is not present in the prior art.
As such, although the prior art has recognized the desirability of using a monolithic design for a focal plane array, the prior art has to date been unable to provide a means of fabricating a dense array of small diameter vias in a wafer which is at least an order of magnitude thicker than the diameter of the vias.